1. Field of the Invention
The present invention relates to a dynamic redundancy circuit for memories in integrated circuit form. It can be used especially in the field of non-volatile memories, notably that of EEPROM type memories. It can also be used in the field of microcontrollers, namely microprocessors that are provided, on one and the same integrated circuit, with a non-volatile memory storing programs or data elements.
2. Discussion of the Related Art
The use of non-volatile-type of memories is presently limited by the number of writing and erasing operations that it is capable of sustaining. A memory cell of this type has, a floating-gate transistor that is charged or discharged with electrical charges or, depending on the binary state to be memorized by the cell. The phenomena by which these dielectric charges undergo leakage and are kept trapped in an insulating region located between the conduction channel of the floating-gate transistor and the floating gate, result in a situation where it becomes increasingly difficult to carry out programming or erasing operations with the aging, deterioration or malfunctioning of the cell. Although modern technology makes it possible to carry out a substantial number of cycles (for example one hundred thousand cycles), this performance is still insufficient in certain cases. In practice, when just one memory cell of such a circuit is affected, the entire circuit has to be discarded.
There are known redundancy circuits and known ways of implementing these circuits. These circuits are used chiefly at the time of the testing of the memory integrated circuits, such as when they are manufactured. To this end, when a memory is manufactured, each of these memory cells is tested one-by-one. When a memory cell in poor condition is detected, for example, because this memory cell cannot be programmed or erased or because it is short-circuited or some other defect, then, the neutralization of this memory cell is prompted, and it is replaced by a supplementary memory cell. This replacement consists in replacing the address of the cell in poor condition by the address of the supplementary replacement cell. This is obtained by a specific operation which includes the opening of certain addressing switches of the integrated circuit and the closing of other switches linked to the foregoing switches. These addressing switches may be formed by fuses. The opening and the closing of these addressing switches are caused by a circuit external to the integrated circuit having the memory. This opening and closing is controlled by software contained in the testing machine. This software takes account of the particular structure of the memory and of its redundancy circuits.
During use, the principle of the programming of the erasure of a memory cell is as follows. When a cell has to be programmed or erased, a microprogram is carried out by an automaton included in the memory. It is aimed at the precharging, with a programming or erasing voltage, of the connections providing access to the cell and then at the selection, by addressing, of the cell to be modified. After this operation, in the case of the EEPROM cells, the cell to be modified is not verified to observe its state. There is no detection, in practice, of the fact that the integrated circuit EEPROM memory needs to be discarded because its operation is no longer reliable.
In the case of the EPROM cells, on the contrary, there are known ways of finding out whether the state obtained after the modification is in accordance with the modified state to be obtained. If necessary, the operation of modification, writing/erasure is repeated a certain number of times. Furthermore the number of attempts is counted. When this number of attempts exceeds a predetermined number, for example, five or six attempts, an automaton of the memory is capable of sending out an error signal to indicate that the concerned memory cell is no longer in proper working condition.